7
Oct

How to use Xilinx Software


hello friends this is the second part of regional tutorial in which we are going to know about xilinx ISE 9.2 I first of all we will get a icon on the screen that is xilinx ISE 9.2 I on which is II is written at the top of the screen ie C stands for integrated system environment double-click on that we will get another window which on which we get the tip of today just click OK on that after that just go on the files and click on the new project to start another project on new project we will get a window on which we need to provide a project name points to remember for giving the project is for the giving the project name is never put this piece and the name never start the project name with a special character or any numeric word after writing the project name just go on click on the next there we will get a properties window on which the product category family device package and speed is selected as per the fpga board if you are using it or leave it like that fe you are not going to implement your project your program on there PG board and after that select the synthesis and simulator tool here it is select as a default synthesis and simulator tool of the xilinx ISE next ensure that you are using the VHDL if preferred language as a VHDL Fe you will go to work on the VHDL like the very log if you are going to work on the very law select the preferred language as per your own preference then click Next there you will get the new source in this window we are going to start a new program or we will going to for a new program window just skip this window right now and click Next there you will get another window on which your each source option if you have any program already returned then just click on the X source and select that file that file will be included in your project then click Next here you are going getting summary of the projects whatever you are selecting till now then click finish if you feel ok and if you want to change something just go to the back and correct the things and then again come here and press the finish button then this type of window occurs on the top you will get the toolbars and menu bar on the extreme left top you will get a window that is known as source window in this window you are getting the names of your files on which you are working and you are working on the past below that source window you will get a window named as process window and this window you are getting the options for checking the syntax RTL view design implement file you see a files and all these things you are getting here and the bottom is the console window on which you are getting the errors and warnings the gree part is the prog-rock agree part is for the program window here we are going to start program to open a program window just click on the I see xe3 yes right click on that select new source then you will get another window there are so many options and we are going to work on the VHDL so select the VHDL module and put the file name here and press next after getting the another window just insert the name of the inputs and outputs and this window and click Next again you will get this summary and if you want to change something just go back else please the button finish now the program window opens here there’s so many things are written on that like the library and entity will come just you need to write the logic and we saw in the previous lecture then that we already we always write the logic in between the architecture and begin and here we are writing C’s assigned to a and B that is the logic for the N gate just save it from the toolbar option always try to select the save all button then go to the synthesis part just opened at a small plus in front of the synthesis access tree and select double click on the check syntax button verify the syntax and if the syntax is correct just go to the view our teal schematic to verify the RTL schematic of the and gate this is the entity declaration box of an gate in the left part you are getting the number of inputs and on the right side you are going to see the number of outputs under clicking this box in the center of this box you will get the logic of that particular program here you are getting the n gate just because you are writing the key word and in your program now this is the hardware part this doesn’t mean that the program works like indeed to ensure that this program will work like a need we need to simulate this program for simulating just good this source window and click on the Seuss button and the bottom of that source window you will get the name of your program just right-click right-click on that and press new Seuss again you will give it the same window that you will get previously for starting the program window here this time you need to select the testbench waveform and give some another name for this test page and press the button next again going next and ensuring that the program is selected for which you are going to write the test bench and then press finish here is the clock window no need to change anything right now just press finish here our testbench waveform window will appear and on this window you will get the number of inputs and outputs just selects the input combination as per your required form like we are going to check the simulation waveform for an gate just select 0 0 0 1 1 0 and 1 1 options and this waveform like we are selecting here and performing all the four operations for the two input and gate and press again save all then going on the source window top of the source window here the source for select behavioral simulation and you will get the dot tvw file select and add just a click on that and go in the process window where you will get a lynx is a simulator open that small plus in front of the Xilinx as a simulator and double-click on the simulate behavioral model there you will get the simulation waveform for and gate you will verify this by clicking anywhere you will get the blue pointer wherever the blue pointer will appear you will get the values of that variables a B and C now and this way you will verify the values of a truth table as per the and gate if it is correct then your program will run on the your program will be correct if you liked this video press like button and subscribe my channel thank you

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